Memory cell sensing circuit with adjusted bias from pre-boost operation
US12394492B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2020 |
| Grant date | Aug 19, 2025 |
| Priority date | — |
| Expiry date | Dec 18, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sense circuit performs a multistage boost, including a boost during precharge operation and a boost during the standard boost operation. The sense circuit includes an output transistor to drive a sense output based on current through a sense node which drives a gate of the output transistor. The sense circuit includes a precharge circuit to precharge the sense node and the gate of the output transistor and a boost circuit to boost the sense node. The boost circuit can be boosted during precharge by a first boost voltage, resulting in a lower boost applied to the sense node after precharge. The boost circuit boosts up the sense node by a second boost voltage lower than the first boost voltage. The boost circuit boosts the sense node down by the full boost voltage of the first boost voltage plus the second boost voltage after sensing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.