Shallow trench isolation spacers
US12394661B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 19, 2022 |
| Grant date | Aug 19, 2025 |
| Priority date | — |
| Expiry date | Oct 9, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for shallow trench isolation spacers are described. In some examples, shallow trenches may be formed in a silicon wafer and one or more dielectric materials may be formed in the trenches. A portion of the dielectric material may subsequently be removed (e.g., etched) and a spacer material may be formed in the trenches. In some examples, portions of the spacer material may be removed (e.g., etched) and the trenches may be filled with the dielectric material. The resulting trench may include one or more spacers that isolate the dielectric material from a gate oxide or other materials formed above the silicon wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.