Time domain analog-to-digital converter and analog-to-digital converting method
US12395183B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 15, 2023 |
| Grant date | Aug 19, 2025 |
| Priority date | — |
| Expiry date | Feb 29, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1245
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In analog-to-digital conversion, a plurality of stages configured in a sequence to sequentially decide a plurality of bits in successive-approximation, each of the plurality of stages configured to operate in response to a corresponding clock among a plurality of clocks, and decide a corresponding bit among the plurality of bits from a corresponding positive pulse among a plurality of positive pulses and a corresponding negative pulse among a plurality of negative pulses; and a plurality of clock generating circuits respectively corresponding to a plurality of first stages among the plurality of stages, each of the plurality of clock generating circuit configured to generate the corresponding clock of a corresponding stage among the plurality of first stages based on an operation of a previous stage among the plurality of stages, the previous stage being before the corresponding stage in the sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.