Reliable link management for a high-speed signaling interconnect
US12395311B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Feb 26, 2024 |
| Grant date | Aug 19, 2025 |
| Priority date | — |
| Expiry date | Feb 26, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/14
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A device includes receiver circuitry to receive incoming signals on a clock lane and data lanes and detection circuitry. The detection circuitry is to monitor the incoming signals on the clock lane, and determine that an incoming pattern of the incoming signals on the clock lane does not correspond to a clock pattern associated with communicating data on the data lanes. The detection circuitry is to initiate a power-down sequence in response to determining that the incoming pattern does not correspond to the clock pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.