3T memory with enhanced speed of operation and data retention
US12396176B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2022 |
| Grant date | Aug 19, 2025 |
| Priority date | — |
| Expiry date | Jan 24, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device including a plurality of memory cells, at least one of the plurality of memory cells includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first drain/source path and a first gate structure electrically coupled to a write word line. The second transistor includes a second drain/source path and a second gate structure electrically coupled to the first drain/source path of the first transistor. The third transistor includes a third drain/source path electrically coupled to the second drain/source path of the second transistor and a third gate structure electrically coupled to a read word line. Where, the first transistor, and/or the second transistor, and/or the third transistor is a ferroelectric field effect transistor or a negative capacitance field effect transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.