PORs testing in multiple power domain devices
US12399218B2 · kind B2 · utility
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16References
20Claims
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Key dates
| Filing date | Feb 7, 2023 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Nov 17, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31721
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to an embodiment, a method for testing multiple power-on-resets in a system-on-chip with a multi-power domain architecture operating under a dual power flow mode is provided. The method includes powering up the system-on-chip to full power mode, decoupling a third power domain from a first power domain and a second power domain, monitoring a general purpose input/output (GPIO) pad of the third power domain during a ramping down of a supply of the third power domain, and detecting a logic transition at the GPIO pad of the third power domain corresponding to a trip-point of the power-on-reset of the third power domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.