Systolic array having support for output sparsity

US12399685B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Jorge Parra · Cameron Park, US
• Fangwen Fu · Folsom, US
• Subramaniam Maiyuran · Citrus, US
• Varghese George · Folsom, US
• Mike B. Macpherson · Portland, US
• Supratim Pal · Bengaluru, IN
• Chandra Gurram · Folsom, US
• Sabareesh Ganapathy · Santa Clara, US
• Sasikanth Avancha · Bengaluru, IN
• Dharma Teja Vooturi · Jagtial, IN
• Naveen Mellempudi · Kanchinakote, IN
• Dipankar Das · Pune, IN

Key dates

• Filing date: Jun 25, 2021
• Grant date: Aug 26, 2025
• Expiry date: Dec 9, 2043

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F7/5443
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A processing apparatus is described herein that includes a general-purpose parallel processing engine comprising a matrix accelerator including one or more systolic arrays, at least one of the one or more systolic arrays comprising multiple pipeline stages, each pipeline stage of the multiple pipeline stages including multiple processing elements, the multiple processing elements configured to perform processing operations on input matrix elements based on output sparsity metadata. The output sparsity metadata indicates to the multiple processing elements to bypass multiplication for a first row of elements of a second matrix and multiply a second row of elements of the second matrix with a column of matrix elements of a first matrix.