Interleaved codeword transmission for a memory device
US12399777B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2024 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | May 8, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for memory operations are described. A first code for detecting one or more errors in a first set of bits of data and a second code for detecting one or more errors in a second set of bits of data may be generated. The first set of bits and the second set of bits may be transmitted over a channel between a memory device and a host device in an interleaved pattern. The first code and the second code may also be transmitted over the channel. The first set of bits and the second set of bits may be deinterleaved by the receiving device. The first set of bits and the second set of bits may also be processed by the receiving device using the first code and the second code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.