Translation lookaside buffer (TLB) prefetcher with multi-level TLB prefetches and feedback architecture
US12399837B2 · kind B2 · utility
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Key dates
| Filing date | May 30, 2023 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Jun 19, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described is a translation lookaside buffer (TLB) prefetcher with multi-level TLB prefetches and feedback architecture. A processing system includes two or more translation lookaside buffer (TLB) levels, each TLB level including a miss queue, and a TLB prefetcher connected to each of the two or more TLB levels. The TLB prefetcher configured to receive feedback from the miss queue at each TLB level for previously sent TLB prefetches and control number of TLB prefetches sent for a trained TLB entry to each TLB level of the two or more TLB levels based on the feedback.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.