Memory device and manufacturing method and test method of the same
US12400692B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2022 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | May 3, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided, including following operations: activating a first word line to couple a first bit line with a second bit line to form a first conductive loop through a first transistor having a first terminal coupled to the first bit line and a second transistor having a first terminal coupled to the second bit line, wherein second terminals of the first and second transistors are coupled together; activating a second word line to couple a third bit line with a fourth bit line to form a second conductive loop, wherein the first and second word lines are disposed below the first to fourth bit lines; and identifying that the first conductive loop, the second conductive loop, or the combinations thereof is short-circuited or open-circuited.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.