Device and method for reading data from memory cells
US12400707B2 · kind B2 · utility
0Cited by
7References
18Claims
0Family size
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Inventor
Key dates
| Filing date | Oct 5, 2021 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Jun 25, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a memory array. The memory array includes a plurality of bitlines. The bitlines are each coupled to a respective local I/O circuit. All of the local I/O circuits are coupled to a global I/O circuit. Each local I/O circuit includes a first sensing stage for reading data from the memory cell. The global I/O circuit includes a second sensing stage for reading data from the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.