Semiconductor packages and methods of manufacturing thereof
US12400983B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2022 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Nov 19, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1434
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a first wafer comprising a first substrate, a first device structure, and a first bonding layer having a pattern of first bonding pads. The first bonding layer is disposed over the first substrate and the first device structure. The semiconductor package includes a second wafer comprising a second substrate, a second device structure, and a second bonding layer having a pattern of second bonding pads. The second bonding layer is disposed over the first bonding layer. The second device structure is disposed over the second bonding layer. The second substrate is disposed over the second device structure. The first bonding pads are each aligned with a corresponding one of the second bonding pads. The first device structure is electrically coupled to the second device structure, through at least one of the first bonding pads and at least one of the second bonding pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.