3D processor having stacked integrated circuit die
US12401010B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2021 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Jun 4, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K19/201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In this arrangement, several circuit blocks defined on each die (1) overlap with other circuit blocks defined on one or more other dies, and (2) electrically connect to these other circuit blocks through connections that cross one or more bonding layers that bond one or more pairs of dies. In some embodiments, the overlapping, connected circuit block pairs include pairs of computation blocks and pairs of computation and memory blocks. The connections that cross bonding layers to electrically connect circuit blocks on different dies are referred to below as z-axis wiring or connections. This is because these connections traverse completely or mostly in the z-axis of the 3D circuit, with the x-y axes of the 3D circuit defining the planar surface of the IC die substrate or interconnect layers. These connections are also referred to as vertical connections to differentiate them from the horizontal planar connections along the interconnect layers of the IC dies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.