Semiconductor device having channel regions distributed on two opposite sides of a gate electrode
US12402300B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2022 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Mar 22, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments relate to a semiconductor device and a forming method. The semiconductor device includes: a substrate; a memory array positioned on the substrate and at least including memory cells spaced along a first direction, each of the memory cells including a transistor, the transistor including a gate electrode, channel regions distributed on two opposite sides of the gate electrode along a third direction, and a source region and a drain region distributed on two opposite sides of each of the channel regions along a second direction, the first direction and the third direction being directions parallel to a top surface of the substrate, the first direction intersecting with the third direction, and the second direction being a direction perpendicular to the top surface of the substrate; and a word line extending along the first direction and continuously electrically connected to the gate electrodes spaced along the first direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.