Semiconductor memory device having shield layer between peripheral circuit and cell array structures
US12402301B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2022 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Nov 28, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are semiconductor memory devices and their fabrication methods. The semiconductor memory device comprises a peripheral circuit structure including peripheral circuits on a semiconductor substrate and a first dielectric layer on the peripheral circuits, a cell array structure on the semiconductor substrate, and a shield layer between the peripheral circuit structure and the cell array structure. The cell array structure includes bit lines, first and second active patterns on the bit lines, first word lines that extend in a second direction on the first active patterns, second word lines that extend in the second direction on the second active patterns, data storage patterns on the first and second active patterns, and a second dielectric layer on the semiconductor substrate. A hydrogen concentration of the first dielectric layer is greater than that of the second dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.