Memory devices and methods of forming the same
US12402327B2 · kind B2 · utility
0Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2022 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Oct 5, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/826
Abstract
A memory device includes a transistor and a memory cell. The transistor includes a gate electrode disposed over a substrate and source/drain regions in the substrate beside the gate electrode. The memory cell is disposed over the transistor and includes a bottom electrode electrically connected to one of the source/drain regions, a top electrode disposed over the bottom electrode, and a first bit and a second bit separated from each other and disposed between the bottom electrode and the top electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.