Integrated passive devices
US12402332B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2021 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Oct 13, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10674
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are a device and techniques for fabricating the device. The device may include a top substrate including a plurality of top vias coupled to a first top metal layer that forms a top winding portion of a first inductor. The device also includes a middle substrate including one or more middle metal layers. The top substrate is disposed on the middle substrate. The one or more middle metal layers form a middle winding portion of the first inductor. The device also includes a bottom substrate electrically coupled to the middle substrate opposite the top substrate, where a first bottom metal layer of the bottom substrate forms a bottom winding portion of the first inductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.