Multi gate semiconductor device
US12402400B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2022 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Feb 8, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0128
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device includes a first active pattern having a first lower pattern and a first sheet pattern on the first lower pattern. First gate structures include a first gate electrode. A second active pattern includes a second lower pattern. A second sheet pattern is on the second lower pattern. Second gate structures include a second gate electrode that surrounds the second sheet pattern. A first source/drain recess is between adjacent first gate structures. A second source/drain recess is between adjacent second gate structures. A first source/drain pattern extends along the first source/drain recess. A first silicon germanium filling film is on the first silicon germanium liner. A second source/drain pattern includes a second silicon germanium liner extending along the second source/drain recess. A second silicon germanium filling film is on the second silicon germanium liner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.