Semiconductor integrated circuit device and manufacturing method thereof
US12402406B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 24, 2021 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Apr 11, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/364
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor integrated circuit device including a substrate with a first element region of a P type and a second element region of an N type, a channel active region that extends in the first element region or the second element region, the channel active region including a plurality of channels, a plurality of gate lines that extend in a second direction intersecting and include a gate metal layer, and a gate insulating film in contact with the gate metal layer, a plurality of first spacers on opposite side portions of respective ones of the gate lines, and a plurality of source/drain regions that are between ones of the plurality of gate lines. The channel active region includes a first channel directly on the substrate, and a second channel spaced apart from the first channel and extends into the gate metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.