Multicycle path prediction of reset signals
US12406120B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2022 |
| Grant date | Sep 2, 2025 |
| Priority date | — |
| Expiry date | Apr 9, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for emulation receives a circuit design driven by a primary clock signal. The circuit design includes reset circuitry and sequential circuitry connected to the reset circuitry. The circuit design includes a secondary clock signal that is slower than the primary clock signal. The reset circuitry generates a reset signal that is a function of the secondary clock signal. The secondary clock signal is remodeled at a transition edge of the primary clock signal, and a predicted reset signal is generated subsequent to the reset signal at the transition edge of the primary clock signal. An operation of the circuit design is emulated based on the predicted reset signal such that the predicted reset signal from the reset circuitry propagates through multiple cycles of the primary clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.