Probabilistic computing devices based on stochastic switching in a ferroelectric field-effect transistor
US12406713B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2021 |
| Grant date | Sep 2, 2025 |
| Priority date | — |
| Expiry date | Jan 4, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/2293
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pbit device, in one embodiment, includes a first field-effect transistor (FET) that includes a source region, a drain region, a source electrode on the source region, a drain electrode on the drain region, a channel region between the source and drain regions, a dielectric layer on a surface over the channel region, an electrode layer above the dielectric layer, and a ferroelectric (FE) material layer between the dielectric layer and the electrode layer. The pbit device also includes a second FET comprising a source electrode, a drain electrode, and a gate electrode. The drain electrode of the second FET is connected to the drain electrode of the first FET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.