Lift pin assembly
US12406873B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2022 |
| Grant date | Sep 2, 2025 |
| Priority date | — |
| Expiry date | Dec 19, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/68785
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment according to the disclosure, an apparatus for manipulating substrates in semiconductor processing comprising a plurality of lift pins, comprising a top end and a down end, and configured for the top end can move upward to an UP position and move downward to a DOWN position, wherein the top end supports a wafer, a weight comprising a plurality of lift pin holes and is configured to connect the plurality of lift pins and a plurality of weight supports, each of them are configured to attach to the plurality of lift pins respectively and each of them are to be placed in the plurality of lift pin holes respectively is presented. The embodiment can improve the semiconductor processing efficiency by preventing the lift pins from getting stuck.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.