Display defect monitoring structure
US12406892B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2023 |
| Grant date | Sep 2, 2025 |
| Priority date | — |
| Expiry date | Apr 19, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/18
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A driver structure for an organic light-emitting diode (OLED) device is provided. The driver structure includes a front-end-of-line (FEOL) layer; a back-end-of-line (BEOL) layer disposed on the FEOL layer; and a customer BEOL layer disposed on the BEOL layer. The BEOL layer includes a customer BEOL electrical checking structure. The customer BEOL electrical checking structure has a plurality of memory cells that include a first memory cell vertically aligned with and corresponds to two adjacent pixel regions. The customer BEOL layer includes six bottom structures corresponding to the two adjacent pixel regions and connected in series to form a first electrical path and a second electrical path each electrically connected to the first memory cell. The first memory cell is configured to detect an anomaly of electrical resistance of the first and second electrical path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.