Dielectric slots underneath conductive vias in interconnect structure of semiconductor package and method of forming the same
US12406941B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2022 |
| Grant date | Sep 2, 2025 |
| Priority date | — |
| Expiry date | Oct 7, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/35121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor package includes depositing a first dielectric layer over a carrier substrate. A first metallization pattern is formed over the first dielectric layer. The first metallization pattern has a first opening exposing the first dielectric layer. A second dielectric layer is deposited over the first metallization pattern, forming a dielectric slot through the first metallization pattern by filling the first opening. A second metallization pattern and a third dielectric layer are formed over the second dielectric layer. A through via is formed over the third dielectric layer, so that the dielectric slot is laterally under the through via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.