Ban-Li Wu
20Patents
3h-index
27Co-inventors
55Inventor score
Filing activity: Aug 14, 2018 → Feb 20, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10832985B2 | Sensor package and method | Electricity | 5 | Active |
| US10840227B2 | Under-bump-metallization structure and redistribution layer design for integrated fan-out package with integrated passive device | Electricity | 5 | Active |
| US11004786B2 | Package structure and method of forming the same | Electricity | 3 | Active |
| US11929318B2 | Package structure and method of forming the same | Electricity | 1 | Active |
| US11374136B2 | Semiconductor package and forming method thereof | Electricity | 1 | Active |
| US10861841B2 | Semiconductor device with multiple polarity groups | Electricity | 1 | Active |
| US11011501B2 | Package structure, package-on-package structure and method of fabricating the same | Electricity | 0 | Active |
| US11842993B2 | Semiconductor device with multiple polarity groups | Electricity | 0 | Active |
| US11742254B2 | Sensor package and method | Electricity | 0 | Active |
| US12015017B2 | Package structure, package-on-package structure and method of fabricating the same | Electricity | 0 | Active |
| US12362274B2 | Package structure and method of forming the same | Electricity | 0 | Active |
| US12261092B2 | Semiconductor package and manufacturing method thereof | Electricity | 0 | Active |
| US11631658B2 | Under-bump-metallization structure and redistribution layer design for integrated fan-out package with integrated passive device | Electricity | 0 | Active |
| US11855232B2 | Semiconductor package and forming method thereof | Electricity | 0 | Active |
| US10658348B2 | Semiconductor devices having a plurality of first and second conductive strips | Electricity | 0 | Active |
| US11527525B2 | Semiconductor device with multiple polarity groups | Electricity | 0 | Active |
| US12205860B2 | Sensor packages | Electricity | 0 | Active |
| US11049850B2 | Methods of bonding the strip-shaped under bump metallization structures | Electricity | 0 | Active |
| US12406941B2 | Dielectric slots underneath conductive vias in interconnect structure of semiconductor package and method of forming the same | Electricity | 0 | Active |
| US12334434B2 | Package structure and method of forming the same | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.