Coding circuit and memory device including the same
US12407366B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Mar 28, 2024 |
| Grant date | Sep 2, 2025 |
| Priority date | — |
| Expiry date | Apr 24, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1515
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A coding circuit includes an encoder circuit that generates parity by applying input data to a parity generating matrix and generate input codeword by concatenating the input data and the parity, and a decoder circuit that detects and corrects an out-of-boundary 2-bit error using syndromes. The out-of-boundary 2-bit error corresponds to two 1-bit errors occurred at two symbols respectively among a plurality of symbols included in output codeword, and the syndromes are generated by applying the output codeword to the parity generating matrix.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.