Differential pair inner-side impedance compensation
US12408263B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 17, 2022 |
| Grant date | Sep 2, 2025 |
| Priority date | — |
| Expiry date | Dec 17, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09236
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An information handling system includes first and second differential pairs on a printed circuit board. The first differential pair includes first and second traces, and first and second sets of impedance compensation traces. The first impedance compensation traces are routed only on an inner-side of the first trace. The second impedance compensation traces are routed only on an inner-side of the second trace, and the first and second impedance compensation traces are substantially aligned. The second differential pair includes third and fourth traces and third and fourth sets of impedance compensation traces. The third set of impedance compensation traces are routed only on an inner-side of the third trace. The fourth impedance compensation traces are routed only on an inner-side of the fourth trace, and the third and fourth impedance compensation traces are substantially aligned.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.