Semiconductor memory device
US12408324B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2022 |
| Grant date | Sep 2, 2025 |
| Priority date | — |
| Expiry date | Dec 16, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6755
Abstract
A semiconductor memory device includes a substrate, a conductive line extending in a first horizontal direction above the substrate, an isolation insulating layer including a channel trench extending in a second horizontal direction intersecting with the first horizontal direction and extending from an upper surface to a lower surface of the isolation insulating layer, above the conductive line, a channel structure disposed above the conductive line, a gate electrode extending in the second horizontal direction, in the channel trench, a capacitor structure above the isolation insulating layer, and a contact structure interposed between the channel structure and the capacitor structure, wherein the channel structure includes an amorphous oxide semiconductor layer disposed in the channel trench above the conductive line, and an upper crystalline oxide semiconductor layer interposed between the amorphous oxide semiconductor layer and the contact structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.