Semiconductor memory device
US12408330B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2022 |
| Grant date | Sep 2, 2025 |
| Priority date | — |
| Expiry date | Sep 6, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
Abstract
A semiconductor memory device includes a substrate including memory cell, peripheral, and intermediate regions; a device isolation pattern; a partitioning pattern; bit lines extending in a first direction to a boundary between the intermediate and peripheral regions; storage node contacts on the memory cell region and filling a lower portion of a space between bit lines; landing pads on the storage node contacts; dummy storage node contacts on the intermediate region and filling a lower portion of a space between bit lines; dummy landing pads on the dummy storage node contacts; and a dam structure on the intermediate region, extending in the first direction, and having a bar shape, wherein the dummy landing pads are spaced apart from an edge of the dam structure in a second direction, and the dummy storage node contacts are in contact with the partitioning pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.