Patent · US Active

Field effect transistor with stacked unit subcell structure

US12408403B2 · kind B2 · utility

0Cited by
17References
31Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJun 24, 2022
Grant dateSep 2, 2025
Priority date
Expiry dateFeb 17, 2044

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D64/254

Abstract

A transistor device includes a first unit subcell including having a first active region width extending in a first direction, and a second unit subcell having a second active region width extending in the first direction and arranged adjacent the first unit subcell in the first direction. The first unit subcell and the second unit subcell share a common drain contact and have separate gate contacts that are aligned in the first direction. Each unit subcell includes a field plate that is connected to a source contact outside the active region and that does not cross over the gate contact.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.