Forksheet semiconductor structure including at least one bipolar junction transistor and method
US12408417B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2022 |
| Grant date | Sep 2, 2025 |
| Priority date | — |
| Expiry date | Mar 25, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are a forksheet semiconductor structure and a method of forming the structure. The structure can include a dielectric body with a first sidewall and a second sidewall opposite the first sidewall. The structure can include a first transistor, which incorporates first semiconductor nanosheet(s) positioned laterally immediately adjacent to the first sidewall of the dielectric body, and a second transistor, which incorporates second semiconductor nanosheet(s) positioned laterally immediately adjacent to the second sidewall. The first transistor and the second transistor can both be bipolar junction transistors (BJTs) (e.g., PNP-type BJTs, NPN-type BJTs or a PNP-type BJT and an NPN-type BJT). Alternatively, the first transistor can be a BJT (e.g., a PNP-type BJT or an NPN-type BJT) and the second transistor can be a field effect transistor (FET) (e.g., an N-type FET (NFET) or a P-type FET (PFET)).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.