Patent · US Active

Integrated circuit structures with backside gate cut or trench contact cut

US12408422B2 · kind B2 · utility

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10Claims

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Assignee

Intel Corporation · US

Inventors

Leonard P. GULER · Hillsboro, US
Charles H. Wallace · Portland, US
Tahir Ghani · Portland, US

Key dates

Filing date	Jun 7, 2021
Grant date	Sep 2, 2025
Priority date	—
Expiry date	Jan 4, 2044

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/0135
WIPO fieldMicro-structural and nano-technology
WIPO sectorChemistry

Abstract

Integrated circuit structures having backside gate cut or backside trench contact cut, and methods of fabricating integrated circuit structures having backside gate cut or backside trench contact cut, are described. For example, an integrated circuit structure includes a first sub-fin structure over a first stack of nanowires. A second sub-fin structure is over a second stack of nanowires. A first gate electrode is around the first stack of nanowires. A second gate electrode is around the second stack of nanowires. A dielectric structure is between the first gate electrode and the second gate electrode. The dielectric structure is continuous along an entirety of a height of the first gate electrode and the first sub-fin structure.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.