Semiconductor structure with frontside port and cavity features for conveying sample to sensing element
US12411105B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2022 |
| Grant date | Sep 9, 2025 |
| Priority date | — |
| Expiry date | Feb 11, 2044 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB01L2300/0645
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A structure includes a lab-on-chip (LOC) sensor and frontside port and cavity features for conveying a flowable sample (fluid or gas) to a sensing element of the sensor. The cavity is confined within middle of the line (MOL) dielectric layer(s). Alternatively, the cavity includes a lower section within MOL dielectric layer(s), an upper section within back end of the line (BEOL) dielectric layer(s) in the first metal (M1) level, a divider between the sections, and a duct linking the sections. Alternatively, the cavity includes a lower portion within MOL dielectric layer(s) and an upper portion continuous with the lower portion and within BEOL dielectric layer(s) in the M1 level. Optionally, the cavity is separated from the sensing element by an additional dielectric layer and/or at least partially lined with a dielectric liner. The port extends from the top of the BEOL dielectric layers down to the cavity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.