Patterning semiconductor features
US12411412B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2022 |
| Grant date | Sep 9, 2025 |
| Priority date | — |
| Expiry date | Jun 5, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/40
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
In certain embodiments, a method includes forming, by photolithography on a semiconductor wafer, first patterned features (PFs) including first photoresist structures (PRSs) having a first width and first recesses having a second width less than the first width and greater than a target width; forming, via anti-spacer patterning processing, second PFs including second PRSs having a third width less than the first width, first overcoat structures (OCSs) of the second width interspersed between second PRSs, and second recesses having a fourth width less than the target width; and forming, via acid diffusion processing, third PFs including third PRSs having a fifth width, second OCSs of the target width interspersed between third PRSs, and third recesses defined by third PRSs and second OCSs and having a sixth width greater than the fourth width, portions of first OCSs having been selectively removed using the acid diffusion processing to form second OCSs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.