Memory device and operating method thereof
US12411603B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2023 |
| Grant date | Sep 9, 2025 |
| Priority date | — |
| Expiry date | Dec 5, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device may include: a plurality of memory cells; a data manager for receiving data from the plurality of memory cells, and generating sub-data groups having a predetermined size, based on the received data; and a data compressor for detecting first-value bits having a first logic value among the bits in the received data, determining a number of target bits corresponding to each of the sub-data groups among the first-value bits to become 1 or less per sub-data group, and generating a plurality of compressed-data chunks including a logic value of the target bits and position information representing a position of the target bits in the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.