Memory device and its operating method, memory system and operating method thereof
US12411609B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2024 |
| Grant date | Sep 9, 2025 |
| Priority date | — |
| Expiry date | Mar 16, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one aspect of the present disclosure, a memory device is provided. The memory device may include an array of memory cells, including a plurality of memory cells. A preset number of memory cells form a code word. The memory device may include peripheral circuit coupled to the array of memory cells. The peripheral circuit may be configured to obtain the first result corresponding to the code word at the target read voltage. The peripheral circuit may be configured to adjust the target read voltage in accordance with the first result corresponding to the code words at the target read voltage. The peripheral circuit may be configured to obtain the first result corresponding to the code words at the adjusted read voltage. The peripheral circuit may be configured to determine a valley voltage in accordance with a plurality of the first results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.