Memory chip test pad access management to facilitate data security
US12411619B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 16, 2022 |
| Grant date | Sep 9, 2025 |
| Priority date | — |
| Expiry date | Sep 16, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for providing memory chip test pad access management to facilitate data security is disclosed. A host issues a command to access a non-volatile memory of a memory chip system via a test pad. A controller acknowledges the command by transmitting a response to the host to authenticate the host for access. The host then issues an authenticated command to modify a reserved byte of a protected memory partition of the non-volatile memory. The controller responds to the authenticated command and the reserved byte is modified. Firmware of the memory chip system monitors the modification of the reserved byte and notifies the memory chip system to activate a switch in an access control unit controlling access to the non-volatile memory. The switch is then activated, thereby closing a circuit to connect the test pad with the non-volatile memory. The host then access the non-volatile memory via the test pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.