Semiconductor device with a vertical channel wrapped around gate, and method for manufacturing the same
US12414288B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2022 |
| Grant date | Sep 9, 2025 |
| Priority date | — |
| Expiry date | Jan 8, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
Abstract
A semiconductor device includes a transistor that is disposed on a substrate. The transistor includes a gate electrode located over the substrate, a gate dielectric disposed on the gate electrode, a channel layer disposed on the gate dielectric, a first source/drain contact disposed on the channel layer and located on a side of the channel layer that is opposite to the substrate, and a second source/drain contact disposed on the channel layer and located on a side of the channel layer that faces the substrate. One of the gate dielectric and the channel layer at least partially surrounds the other one of the gate dielectric and the channel layer. A region of the channel layer between the first source/drain contact and the second source/drain contact is elongated in a direction perpendicular to the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.