Forming low-resistance capping layer over metal gate electrode
US12414329B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2022 |
| Grant date | Sep 9, 2025 |
| Priority date | — |
| Expiry date | May 23, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/01
Abstract
A semiconductor device includes stacks of nano-structures that each extend in a first horizontal direction. The stacks each extend in a vertical direction and are separated from one another in a second horizontal direction. A first gate is disposed over a first subset of the stacks. A second gate is disposed over a second subset of the stacks. A first conductive capping layer is disposed over a substantial entirety of an upper surface of the first gate. A second conductive capping layer is disposed over a substantial entirety of an upper surface of the second gate. A dielectric structure is disposed between the first gate and the second gate in the second horizontal direction. The dielectric structure physically and electrically separates the first gate and the second gate. An upper surface of the dielectric structure is substantially free of having the first or second conductive capping layers disposed thereon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.