Isolation for multigate devices
US12414331B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2022 |
| Grant date | Sep 9, 2025 |
| Priority date | — |
| Expiry date | Nov 8, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
An exemplary device includes a stack of channel layers over a substrate extension, a gate, and an insulation layer. The stack of channel layers extends between a first epitaxial source/drain and a second epitaxial source/drain. The gate surrounds each channel layer of the stack of the channel layers. The insulation layer is over the substrate extension, the gate is between a bottommost channel layer of the stack of channel layers and the insulation layer, and the insulation layer is between the gate and the substrate extension. The insulation layer extends between the first epitaxial source/drain and the second epitaxial source/drain, each of which may include an undoped epitaxial layer. A top surface of the undoped epitaxial layer is below a bottom surface of the bottommost channel layer and/or above a top surface of the insulation layer. The insulation layer may wrap the substrate extension and/or have an air gap therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.