Detection of data corruption in memory address decode circuitry
US12417042B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Dec 2, 2021 |
| Grant date | Sep 16, 2025 |
| Priority date | — |
| Expiry date | Jan 17, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1474
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller including memory address decode circuitry that detects silent data errors that occur in the memory address decode circuitry during runtime is provided. The memory address decode circuitry includes address decode circuitry to covert a received physical address to a memory address, reverse address decode circuitry to convert the memory address to a second physical address and address compare circuitry to compare the received physical address and the second physical address to detect a silent error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.