Inventor · Los Altos, CA, US

Sreenivas Mandava

13Patents

2h-index

31Co-inventors

46Inventor score

Filing activity: Dec 18, 2013 → Dec 2, 2021

Most-cited inventions

Patent	Title	Area	Cited by	Status
US9449671B2	Techniques for probabilistic dynamic random access memory row repair	Emerging Cross-Sectional Technologies	11	Active
US9269436B2	Techniques for determining victim row addresses in a volatile memory	Physics	5	Active
US9824754B2	Techniques for determining victim row addresses in a volatile memory	Physics	2	Active
US10102886B2	Techniques for probabilistic dynamic random access memory row repair	Emerging Cross-Sectional Technologies	2	Active
US10162761B2	Apparatus and method for system physical address to memory module address translation	Physics	1	Active
US12321622B2	Deferred ECC (error checking and correction) memory initialization by memory scrub hardware	Physics	0	Active
US10552643B2	Fast boot up memory controller	Physics	0	Active
US12099388B2	Temperature-based runtime variability in victim address selection for probabilistic schemes for row hammer	Physics	0	Active
US9747041B2	Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device	Emerging Cross-Sectional Technologies	0	Active
US12235720B2	Adaptive error correction to improve system memory reliability, availability, and serviceability (RAS)	Physics	0	Active
US12417042B2	Detection of data corruption in memory address decode circuitry	Physics	0	Active
US10042562B2	Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device	Emerging Cross-Sectional Technologies	0	Active
US12347507B2	Method and apparatus for memory chip row hammer threat backpressure signal and host side response	Physics	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.