Adaptive system probe action to minimize input/output dirty data transfers
US12417179B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2023 |
| Grant date | Sep 16, 2025 |
| Priority date | — |
| Expiry date | Dec 28, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Adaptive system probe action to minimize input/output dirty data transfers is described. In one or more implementations, a system includes a processor, a memory configured to store data, and a cache configured to store a portion of the data stored in the memory for execution by the processor. The system also includes a cache coherence controller including a cache line history. The cache coherence controller is configured detect a direct memory access request from an input/output device. The direct memory access request is associated with an input/output operation involving the data. The cache coherence controller is further configured to identify a cache line associated with the direct memory access request, and, in response to the cache line history including a dirty data transfer record corresponding to the cache line, selectively send a probe to the cache based on a state of the cache line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.