Multi-chip secure and programmable systems and methods
US12417319B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2023 |
| Grant date | Sep 16, 2025 |
| Priority date | — |
| Expiry date | Apr 25, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/63
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various techniques are provided to implement multi-chip secure and programmable systems and methods. In one example, a multi-chip module system for providing an integrated programmable logic functionality and security functionality. The multi-chip module system includes a first die including a programmable logic device (PLD) configured to provide at least a portion of the programmable logic functionality. The multi-chip system further includes a second die including a security engine configured to perform at least a portion of the security functionality. The security engine is further configured to receive, from the first die, data associated with a first and second configuration image; perform a read operation on a memory for the second configuration image based on the data; and authenticate the second configuration image. The multi-chip system further includes a configuration engine configured to program the PLD according to the first configuration image. Related devices and methods are provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.