Method for producing a superconducting vanadium silicide on a silicon layer
US12417919B2 · kind B2 · utility
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10Claims
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Key dates
| Filing date | Aug 31, 2022 |
| Grant date | Sep 16, 2025 |
| Priority date | — |
| Expiry date | Dec 28, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N60/128
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for producing a superconducting vanadium silicide on a silicon layer includes treating a face of the silicon layer in order to prepare it for a deposition of vanadium silicide, then depositing a vanadium silicide layer on the prepared face of the silicon layer in order to obtain a stack of a vanadium silicide layer directly deposited on the silicon layer, then an annealing the stack which increases the critical temperature of the vanadium silicide deposited. The treating includes an operation of incorporation of argon atoms in the silicon layer through the face of the silicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.