Formation of self-assembled monolayer for selective etching process
US12417924B2 · kind B2 · utility
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Key dates
| Filing date | Jan 12, 2023 |
| Grant date | Sep 16, 2025 |
| Priority date | — |
| Expiry date | Mar 21, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31138
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A selective etching process includes treating a first dielectric region and a second dielectric region of a semiconductor device with a self-assembled-monolayer-forming compound to form a self-assembled monolayer to selectively cover the first dielectric region so as to expose the second dielectric region; and selectively etching the second dielectric region using a dilute acid solution while the first dielectric region is protected by the self-assembled monolayer from being etched by the dilute acid solution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.