Semiconductor structure and manufacturing method thereof
US12419033B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 1, 2022 |
| Grant date | Sep 16, 2025 |
| Priority date | — |
| Expiry date | Jan 12, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
Abstract
Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base; a bit line; a word line; an active pillar, wherein the active pillar includes a source region, a channel region, and a drain region, the bit line is connected to one of the source region and the drain region of the active pillar, and the word line surrounds the channel region of the active pillar; a plurality of memory structures, wherein the memory structure is located between adjacent isolation layers, the memory structure includes a first electrode plate, a medium layer, and a second electrode plate that are sequentially stacked, the medium layer is located between the first electrode plate and the second electrode plate, the first electrode plate is connected to the other of the source region and the drain region of the active pillar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.