Methods of forming transistor source/drain regions comprising carbon liner layers
US12419084B2 · kind B2 · utility
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Key dates
| Filing date | Dec 30, 2021 |
| Grant date | Sep 16, 2025 |
| Priority date | — |
| Expiry date | Aug 2, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/017
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
In an embodiment, a device includes: a first nanostructure; a source/drain region adjoining a first channel region of the first nanostructure, the source/drain region including: a main layer; and a first liner layer between the main layer and the first nanostructure, a carbon concentration of the first liner layer being greater than a carbon concentration of the main layer; an inter-layer dielectric on the source/drain region; and a contact extending through the inter-layer dielectric, the contact connected to the main layer, the contact spaced apart from the first liner layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.