Portioned erase operation for a memory system
US12422987B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2023 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | Dec 14, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for an erase operation for a memory system are described. The memory system may perform, on a block of memory cells, a first portion of an erase operation. After performing the first portion of the erase operation, the memory system may receive a write command to write data to the block of memory cells. In response to receiving the write command, the memory system may determine whether a threshold voltage of the block of memory cells satisfies a threshold. In response to determining the that the threshold voltage satisfies the threshold, the memory system may perform a second portion of the erase operation on the block of memory cells. As such, the memory system may write the data to the block of memory cells in response to performing the second portion of the erase operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.