Host, memory system, and operation methods thereof
US12423005B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2024 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | Jun 7, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In certain aspects, a host is disclosed. The host includes a memory configured to store instructions and a processor coupled to the memory. Responsive to execution of the instructions, the processor is configured to determine a power-up event after abnormal power-off and perform a roll-forward recovery for a memory system. A set of node blocks to be recovered is determined. For each node block included in the set of node blocks, a first data block stored in the memory system is determined based on the node block. It is determined whether first node address information retrieved from a metadata part of the first data block matches second node address information of the node block. It is determined whether to recover the node block and the first data block in the memory system based on whether the first node address information matches the second node address information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.